premier prototype Talas One fonctionnel : doc complète, tests audio, projets KiCad p2
Premier enregistrement audio fonctionnel (canal B, capsule SC600, bodges). Documentation de l'état exact du prototype (ETAT_PROTOTYPE_P1.md), liste des corrections pour les PCBs p3/p2 (CORRECTIONS_PCB_P2.md), rapport de bug preamp (RAPPORT_BUG_PREAMP_P1.pdf), projets KiCad preamp p2 + hex inverter p2, captures Rigol, et 20 enregistrements WAV de test (10-12 avril 2026). Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
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# Corrections PCB — Prochaines versions (preamp p3 + hex inverter p2)
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> **Date : 12 avril 2026**
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> Base sur le debug du prototype P1 (10-12 avril 2026).
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> Etat actuel documente dans [[02_PRODUITS_PHYSIQUES/Microphone/Conception/ETAT_PROTOTYPE_P1]]
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> Rapport de bug detaille : [[02_PRODUITS_PHYSIQUES/Microphone/Conception/RAPPORT_BUG_PREAMP_P1.pdf]]
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---
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## 1. Carte preamp — p3 (PRIORITAIRE)
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### 1.1 Bugs critiques a corriger (3 par canal, 6 au total)
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Ces 3 erreurs sont documentees en detail dans le RAPPORT_BUG_PREAMP_P1.pdf. Elles proviennent d'une confusion entre pin 2 (-) et pin 3 (+) causee par le symbole SnapEDA OPA1642 qui place (-) en haut et (+) en bas.
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#### Canal A (IC1) — memes corrections pour canal B (IC2)
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| # | Erreur actuelle (p1) | Correction p3 | Impact |
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|---|---------------------|---------------|--------|
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| 1 | SGNL_A1 connecte a IC1 **pin 2** (inverseur) | Deplacer SGNL_A1 vers IC1 **pin 3** (non-inverseur) | Signal entre sur la bonne entree du voltage follower |
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| 2 | Aucun fil entre pin 1 (sortie) et pin 2 (inverseur) | Ajouter un wire **pin 1 → pin 2** (feedback direct) | Ferme la boucle de contre-reaction, gain = +1 (suiveur) |
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| 3 | R9 relie pin 3 (entree +) a pin 6 (entree - IC1B) | Deplacer R9 : **pin 1** (sortie IC1A) → pin 6 (entree - IC1B) | L'inverseur IC1B recoit le signal de sortie d'IC1A |
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#### Canal B (IC2) — identique
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| # | Correction |
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|---|-----------|
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| 1 | SGNL_B1 : pin 2 → **pin 3** |
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| 2 | Ajouter wire **pin 1 → pin 2** |
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| 3 | R19 : pin 3 → **pin 1** vers pin 6 |
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### 1.2 Bug mineur a corriger
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| # | Probleme | Correction | Priorite |
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|---|----------|-----------|----------|
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| 4 | Deux nets de masse distincts (`GND` et `Earth`) dans le schema KiCad | Unifier en un seul symbole de masse pour tous les condensateurs de decouplage | Basse (probablement ponte par le cuivre sur le PCB, mais sale dans le schema) |
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| 5 | Labels VCC_A1/VCC_A2 inverses par rapport a la convention AliceOPA (VCC_A1 = rail phantom brut, VCC_A2 = rail regule 12V) | Renommer pour cohérence avec la doc DJJules : VCC_1 = rail regule, VCC_2 = rail intermediaire | Cosmetique |
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### 1.3 Ameliorations optionnelles
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| # | Amelioration | Justification | Priorite |
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|---|-------------|---------------|----------|
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| 6 | R5/R15 : 200 Ohm → 330 Ohm | Alignement avec la reference dual-channel DJJules. Impact marginal (~0.4V de chute supplementaire) | Basse |
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| 7 | Ajouter des trous de montage ou des temoins LED pour les rails VCC | Facilite le debug des futurs prototypes | Basse |
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### 1.4 Procedure de correction dans KiCad
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```
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1. Ouvrir mic_preamp_pcb_prototype_p1.kicad_sch
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2. Pour IC1 (canal A) :
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a. Supprimer le wire entre SGNL_A1 et pin 2
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b. Creer un wire entre SGNL_A1 et pin 3
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c. Creer un wire entre pin 1 (sortie) et pin 2 (feedback)
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d. Supprimer le wire R9-pin1 → pin 3
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e. Creer un wire R9-pin1 → pin 1 (sortie)
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3. Repeter pour IC2 (canal B) avec SGNL_B1 et R19
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4. Unifier les symboles de masse (GND + Earth → un seul)
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5. Lancer ERC — verifier 0 erreur
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6. Mettre a jour le PCB (Update PCB from schematic)
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7. Re-router les 6 pistes modifiees (ou autorouter)
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8. Exporter gerbers
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9. Commander sur JLCPCB (~5 EUR, 10-14 jours)
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```
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> **IMPORTANT** : avant de router, activer l'affichage des numeros de pins dans le schema pour verifier visuellement que chaque signal arrive bien sur la bonne pin physique. Ne plus se fier a la position visuelle haut/bas du symbole.
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---
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## 2. Carte hex inverter — p2
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### 2.1 Bugs critiques de routage (2 bodges necessaires sur p1)
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| # | Bug | Consequence sur p1 | Correction p2 |
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|---|-----|-------------------|---------------|
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| 1 | **Pad VCC entree (mid_ctr) et pad VDD chip (mid_right) sur 2 nets separes** — pas de piste cuivre entre les deux | TC4584BF pin 14 a 0.25V au lieu de 12V. Oscillateur ne demarre pas. POL = 0V | Router une piste F_Cu ou B_Cu entre mid_ctr et mid_right |
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| 2 | **Pin 7 (VSS) du TC4584BF non routee vers GND** — aucune piste sur aucune couche | Le chip n'a pas de reference de masse. Comportement imprevisible | Router pin 7 vers le pad GND1 |
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### 2.2 Bug composant
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| # | Bug | Correction p2 |
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|---|-----|---------------|
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| 3 | **D8 (protection entree)** — orientation ambigue dans le schema, la diode bloquait le VCC entrant | Clarifier l'orientation dans le schema. Alternativement, remplacer D8 par un simple jumper si la protection n'est pas necessaire |
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### 2.3 Ameliorations recommandees
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| # | Amelioration | Justification | Priorite |
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|---|-------------|---------------|----------|
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| 4 | **Augmenter le nombre d'etages Cockcroft-Walton** | La tension POL actuelle (25-28V mesure a vide) est suffisante pour la SC600 mais insuffisante pour la CY002 (40-60V requis). Passer de 6 a 8 ou 10 etages | Haute (si on veut utiliser la capsule CY002 definitive) |
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| 5 | **Reduire R1 de 1 GOhm a une valeur plus basse** (ex: 10 MOhm ou 100 MOhm) | R1 = 1 GOhm cree un filtre avec une constante de temps enorme et rend la mesure POL impossible au multimetre. La reference AliceOPA utilise aussi 1 GOhm mais dans un contexte avec plus d'etages CW | Moyenne — a evaluer, la valeur actuelle fonctionne |
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| 6 | **Ajouter un condensateur de decouplage supplementaire** entre VDD (pin 14) et VSS (pin 7) directement sur le PCB, pres du chip | Stabilise l'oscillateur, reduit le bruit HF | Haute |
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| 7 | **Ajouter les orientations des diodes sur la serigraphie** | Eviter l'erreur de soudage a l'envers (toutes les 8 diodes etaient a l'envers sur p1) | Haute |
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| 8 | **Ajouter une serigraphie claire pour les 3 gros pads** (VCC / GND / POL) | Sur p1 il n'etait pas evident quel pad correspondait a quoi | Moyenne |
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### 2.4 Schema de la cascade corrige (reference pour p2)
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```
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Oscillateur (TC4584BF pin 12/13)
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│
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├──C──► D1 ──C──► D2 ──C──► D3 ──C──► D4 ──C──► D5 ──C──► D6 ──► POL
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│ │
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│ (sens des diodes : cathode vers POL, toutes dans le meme sens) │
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│ │
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└── GND (reference) R1 (1G)
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│
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Capsule
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│
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GND
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D8 (entree VCC) : anode vers VCC externe, cathode vers VDD chip
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(protection contre inversion de polarite — optionnel)
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```
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---
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## 3. Composants a commander pour p3 + hex p2
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### Composants neufs necessaires
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| Composant | Quantite | Raison | Fournisseur |
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|-----------|---------|--------|-------------|
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| 1N4742 (zener 12V) | 2 | Remplacer D1 claquee + spare | Mouser / Farnell |
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| OPA1642AID | 2 | IC1 + IC2 pour le nouveau PCB p3 (les actuels sont soudés sur p1) | Mouser |
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### PCBs a commander
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| PCB | Fichier gerber | Fab | Cout estime |
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|-----|---------------|-----|-------------|
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| Preamp p3 | A generer apres correction schema | JLCPCB | ~5 EUR (5 pcs) |
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| Hex inverter p2 | A generer apres correction schema | JLCPCB | ~5 EUR (5 pcs) |
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### Composants reutilisables depuis p1
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Tous les composants passifs du preamp p1 (20 resistances, 14 condensateurs, 2 zeners sauf D1) sont THT et peuvent etre desoudes et remontes sur p3. Les composants du hex inverter (TC4584BF, MC33761, condensateurs, resistances) aussi.
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---
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## 4. Ordre des operations
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```
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Phase 1 — Correction schemas (1 session, ~2h)
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├── Corriger mic_preamp_pcb_prototype_p1.kicad_sch (6 wires)
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├── Corriger mic_hex_inverter_pcb_prototype_p1.kicad_sch (routing + orientations)
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├── ERC clean sur les deux schemas
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├── Update PCB from schematic + re-routage
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└── Export gerbers
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Phase 2 — Commande (10-14 jours d'attente)
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├── Commander preamp p3 + hex p2 sur JLCPCB
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├── Commander 1N4742 + OPA1642 neufs si besoin
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└── Pendant l'attente : tests audio qualite sur le proto P1 actuel
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Phase 3 — Assemblage p3 + hex p2 (~1 jour)
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├── Dessouder composants passifs de preamp p1 → remonter sur p3
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├── Dessouder composants hex p1 → remonter sur hex p2
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├── Souder OPA1642 neufs sur p3
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├── Test alimentation (VCC_A1, VCC_B1, VCC_A2, VCC_B2)
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├── Test oscillateur + POL
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├── Test audio complet (2 canaux !)
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└── Montage dans le corps metallique
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Phase 4 — Validation
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├── Tests audio complets (protocole PROTOCOLES_TESTS_HARDWARE.md)
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├── Comparaison A/B vs Vibe C1 et Rode NT1-A
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└── Decision go/no-go pour la capsule CY002
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```
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---
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## Voir aussi
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- [[02_PRODUITS_PHYSIQUES/Microphone/Conception/ETAT_PROTOTYPE_P1]] — Etat actuel du prototype
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- [[02_PRODUITS_PHYSIQUES/Microphone/Conception/RAPPORT_BUG_PREAMP_P1.pdf]] — Analyse detaillee des bugs
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- [[02_PRODUITS_PHYSIQUES/Microphone/Conception/GUIDE_DEBUG_TALAS_ONE]] — Guide de debug
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- [[01_PILOTAGE/ROADMAP_HARDWARE]] — Planning hardware
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- [[02_PRODUITS_PHYSIQUES/Microphone/BOM/COMMANDE_GROUPEE_AVRIL_2026]] — Commande composants
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202
02_PRODUITS_PHYSIQUES/Microphone/Conception/ETAT_PROTOTYPE_P1.md
Normal file
202
02_PRODUITS_PHYSIQUES/Microphone/Conception/ETAT_PROTOTYPE_P1.md
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# Etat du prototype Talas One P1 — Premier prototype fonctionnel
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> **Date : 12 avril 2026**
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> **Statut : FONCTIONNEL (canal B uniquement, avec bodges)**
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> Capsule : t.bone SC600 (dual-diaphragm, un seul diaphragme cable)
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> Interface : Audient iD14 (phantom 48V)
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> Enregistrement de reference : `tests/final_first_win_nobridgeD6POL_noparallelcondenser.wav`
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---
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## 1. Resume
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Le Talas One P1 produit du son pour la premiere fois le 12 avril 2026 apres ~2 jours de debug intensif. Le micro fonctionne **uniquement sur le canal B** du preamp (canal A hors service, zener D1 claquee). Plusieurs bodges ont ete necessaires sur les deux PCBs pour compenser des erreurs de conception et de routage. Le montage dans le corps metallique (cage de Faraday) a ete l'etape finale qui a elimine le bruit parasite 50 Hz.
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---
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## 2. Etat de chaque PCB
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### 2.1 Carte preamp OPA (mic_preamp_pcb_prototype_p1)
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#### Canal A — HORS SERVICE
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| Probleme | Detail |
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|----------|--------|
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| D1 zener 12V claquee | Mesure en mode diode : 0.47V dans les deux sens. 326 Ohm entre VCC_A1 et GND. VCC_A1 tombe a 3V au lieu de 12V. |
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| Cause probable | Surcharge lors des multiples sessions de debug avec phantom 48V |
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| Reparation | Remplacer D1 par une 1N4742 (zener 12V) neuve |
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#### Canal B — FONCTIONNEL
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| Point de mesure | Valeur mesuree | Attendu | Statut |
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|-----------------|---------------|---------|--------|
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| XLR pin 2 (X2B1) | 19.81V | ~20V | OK |
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| VCC_B1 (apres zener D2) | 12.49V | 12V | OK |
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| VCC_B2 (GND virtuel) | ~6V | ~6V | OK |
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#### Bug de schema preamp (affecte les 2 canaux)
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Trois erreurs de cablage identifiees dans le schema KiCad `mic_preamp_pcb_prototype_p1.kicad_sch` (voir [[02_PRODUITS_PHYSIQUES/Microphone/Conception/RAPPORT_BUG_PREAMP_P1.pdf]] pour le detail complet) :
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1. **SGNL va sur pin 2 (inverseur) au lieu de pin 3 (non-inverseur)** — le symbole OPA1642 SnapEDA a une disposition (+)/(-) inversee par rapport a la convention standard
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2. **Aucune boucle de contre-reaction sur IC1A/IC2A** — pin 1 (sortie) n'est pas reliee a pin 2, l'op-amp fonctionne en boucle ouverte (gain ~100 000)
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3. **R9/R19 relie pin 3 a pin 6 au lieu de pin 1 a pin 6** — l'inverseur IC1B/IC2B ne recoit aucun signal
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**Pourquoi ca marche quand meme (canal B)** : le signal passe malgre tout car l'op-amp en boucle ouverte agit comme comparateur — le signal de la capsule module la saturation et produit un signal audio degrade mais audible. La qualite n'est pas optimale (distorsion, dynamique limitee), mais suffisante pour valider que la chaine capsule → preamp → XLR → interface fonctionne.
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> **Note** : aucun bodge n'a ete realise sur le preamp pour corriger ces 3 erreurs. Le prototype fonctionne "tel quel" avec les erreurs. La correction sera faite dans le schema KiCad pour le PCB p3.
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### 2.2 Carte hex inverter (mic_hex_inverter_pcb_prototype_p1)
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#### Bodges realises (5 au total)
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| # | Bodge | Raison | Detail |
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|---|-------|--------|--------|
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| 1 | **Toutes les diodes D1-D7 retournees 180 degres** | Installees a l'envers initialement. La direction du pompage Cockcroft-Walton etait inversee → POL = 0V | Desoudees et retournees une par une. D6 a necessite un traitement special (voir #3) |
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| 2 | **D8 bypassee avec un fil** | D8 (diode de protection/entree) defectueuse ou orientation incertaine. Bloquait le passage du 12V vers le chip | Fil soude directement entre les deux pads de D8, court-circuitant la diode |
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| 3 | **Pont mid_ctr → mid_right** | Les deux gros pads de la rangee du milieu sont sur 2 nets separes dans le PCB. Le rail VDD du TC4584BF (pin 14) etait deconnecte du rail VCC d'entree | Fil soude entre le pad central et le pad de droite pour fermer le circuit VDD |
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| 4 | **Pin 7 TC4584BF → GND** | Pin 7 (VSS) du chip n'a aucune piste vers GND sur aucune couche du PCB. Le chip n'avait pas de reference de masse | Fil soude de la pin 7 vers le pad GND1 le plus proche |
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| 5 | **D6 retournee separement** | D6 avait besoin d'une orientation differente des autres diodes dans la cascade (position specifique dans le Cockcroft-Walton) | Retournee apres avoir retourne les autres, mesures oscillo ont confirme le bon fonctionnement |
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#### Mesures validees apres bodges
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| Point de mesure | Valeur | Statut |
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|-----------------|--------|--------|
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| Pin 14 TC4584BF (VDD) | 11.70V | OK (alimente depuis VCC_B1 = 12.49V) |
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| Pin 7 TC4584BF (VSS) | 0V | OK (bodge vers GND) |
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| Signal oscillateur (pin 2, oscillo) | Carre 0-12V, ~76 kHz | OK |
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| Cathode D5/D6 (sommet cascade) | 24-29V (a vide) | OK |
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| POL (multimetre, sous charge capsule) | ~5.6V affiche (reel ~25V via diviseur R1 1G / Zmetre 10M) | OK — la mesure au multimetre est trompeuse, voir note |
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> **Note sur la mesure POL** : le pad POL est derriere une resistance de 1 GOhm (R1). Le multimetre (impedance d'entree 10 MOhm) cree un diviseur de tension qui affiche ~5V quand la tension reelle est ~25V. La methode correcte pour valider POL est le test fonctionnel (signal audio present = capsule polarisee).
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#### Bugs de routage PCB hex inverter (a corriger dans p2)
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| Bug | Impact | Decouvert par |
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|-----|--------|---------------|
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| Pas de piste entre VCC entree et VDD chip (mid_ctr ≠ mid_right) | TC4584BF sans alimentation | Analyse gerber avec union-find sur F_Cu + B_Cu |
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| Pin 7 (VSS) non routee | TC4584BF sans masse | Meme analyse |
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| D8 orientation/routage ambigu | Diode de protection bloquait le VCC | Debug empirique |
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---
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## 3. Capsule et cablage
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### Capsule utilisee
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| | |
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|---|---|
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| **Modele** | t.bone SC600 (achetee sur Thomann) |
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| **Type** | Condensateur large membrane, **dual-diaphragm** (style K67) |
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| **Fils** | 3 fils : 1 noir (GND/body commun), 2 rouges (front + rear diaphragm) |
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| **Capacite mesuree** | ~0.30 nF entre chaque diaphragme et le body |
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| **Montage actuel** | **Single-channel** : 1 seul diaphragme (rear) cable vers SGNL_B1, l'autre flottant |
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### Cablage actuel (configuration fonctionnelle)
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```
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Capsule SC600 (dual-diaphragm)
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├── Fil noir (body/backplate commune) → GND_B1 du preamp
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├── Fil rouge 1 (rear backplate) → SGNL_B1 du preamp (signal)
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└── Fil rouge 2 (front backplate) → NON CONNECTE (flottant)
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POL (sortie hex inverter) → Corps metallique de la capsule (body = backplate commune)
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```
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> **Important** : sur une capsule dual-diaphragm, le corps metallique est la backplate commune. La tension de polarisation (POL) va sur le corps, et le signal est capte sur les backplates individuelles (fils rouges). C'est l'inverse d'une capsule single-diaphragm classique.
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### Configuration finale qui a marche
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- POL connecte normalement via le chemin de filtrage R1 (1 GOhm) du hex inverter (pas de bridge D6→POL)
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- Pas de condensateur en derivation entre GND1 et POL
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- Capsule montee dans le corps metallique du micro (cage de Faraday = suppression du 50 Hz)
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---
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## 4. Corps metallique et montage
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| | |
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|---|---|
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| **Corps** | Style BM-800 generique (AliExpress), aluminium/chrome |
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| **Modele 3D** | `K87+Saddle.stl` (Solidworks) |
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| **Blindage** | Le corps metallique est relie a la masse (XLR pin 1) et forme une cage de Faraday |
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| **Impact critique** | Le montage dans le corps a **elimine le bruit 50 Hz** qui dominait tous les enregistrements precedents. C'est le facteur decisif qui a rendu le micro utilisable |
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### Historique du bruit 50 Hz
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|
||||
Avant le montage dans le corps, tous les enregistrements montraient > 90% de l'energie dans la bande 0-100 Hz (50 Hz secteur). La resistance de bias 1 GOhm agit comme antenne pour le champ electrique ambiant. Plusieurs tentatives de reduction :
|
||||
|
||||
1. Bridge D6 cathode → POL (court-circuiter R1) → amelioration partielle
|
||||
2. Condensateur 100nF en derivation POL-GND → amelioration partielle
|
||||
3. **Montage dans le corps metallique** → **resolution complete** (le corps metallique blinde le circuit haute impedance)
|
||||
|
||||
---
|
||||
|
||||
## 5. Equipement utilise pour le debug
|
||||
|
||||
| Equipement | Usage |
|
||||
|-----------|-------|
|
||||
| Audient iD14 | Interface audio principale, phantom 48V |
|
||||
| Rigol DHO814 | Oscilloscope pour verifier l'oscillateur TC4584BF (76 kHz) et la cascade |
|
||||
| Voltcraft VC-23 | Multimetre pour tensions, continuite, mode diode |
|
||||
| Toolcraft ST-100D | Station de soudage pour les bodges |
|
||||
| Loupe binoculaire | Inspection soudures et composants SOIC |
|
||||
|
||||
---
|
||||
|
||||
## 6. Enregistrements de test (chronologie)
|
||||
|
||||
| Fichier | Date | Description | Etat |
|
||||
|---------|------|-------------|------|
|
||||
| `test-sc600_n1.wav` | 10 avr | Premier branchement, rien d'audible | Preamp alimente, hex inverter mort |
|
||||
| `test-sc600_n2.wav` | 11 avr | Apres inversion de toutes les diodes | Toujours pas d'audio clair |
|
||||
| `test-sc600_n3.wav` | 11 avr | Gain baisse, mesures POL = 0V | Hex inverter encore defaillant |
|
||||
| `test-sc600_n4.wav` | 11 avr | Tests intermediaires | Debug en cours |
|
||||
| `test-sc600_n5.wav` | 11 avr | Bridge D6→POL + cap en derivation | Premier signal avec bruit |
|
||||
| `test-sc600_n6.wav` | 11 avr | Suite tests cascade | POL instable |
|
||||
| `tap_test.wav` | 11 avr | Tapotement sur capsule, verif mecaniquement | Premiere confirmation que le preamp voit un signal |
|
||||
| `test123.wav` | 11 avr | Voix avec gain baisse, capsule sur bois | Voix audible sous le buzzer 50 Hz |
|
||||
| `test-ab.wav` | 11 avr | Test A/B | Comparaison configurations |
|
||||
| `test_final.wav` | 11 avr | Test en conditions ameliorees | Proche du fonctionnel |
|
||||
| `long.wav` | 11 avr | 12 min — cross-test avec Vibe C1 (4 phases) | Test de reference multi-config |
|
||||
| `imrpove1.wav` | 11 avr | Bridge + cap, voix audible sous le bruit | Premiere vraie capture voix |
|
||||
| `imrpove1_cleaned.wav` | 11 avr | Meme fichier filtre (notch 50 Hz) | Voix clairement audible |
|
||||
| **`final_first_win_nobridgeD6POL_noparallelcondenser.wav`** | **12 avr** | **SUCCES — micro monte dans le corps, signal propre** | **Premier prototype fonctionnel** |
|
||||
|
||||
---
|
||||
|
||||
## 7. Captures oscilloscope (Rigol DHO814)
|
||||
|
||||
Toutes dans `tests/rigol_screens/` :
|
||||
|
||||
| Fichier | Ce qu'on voit |
|
||||
|---------|--------------|
|
||||
| `TC4584BF_pin2.jpg` | Signal carre 0-12V sur pin 2 (sortie oscillateur IC1A) |
|
||||
| `TC4584BF_pin2_p2.jpg` | Meme mesure, deuxieme prise |
|
||||
| `TC4584BF_diodes_cascade_p1.jpg` | Signal a travers la cascade (mauvais timebase, 51 Hz apparent) |
|
||||
| `TC4584BF_diodes_cascade_p2.jpg` | Cascade apres correction timebase |
|
||||
| `TC4584BF_diodes_cascade_pin13_p1.jpg` | Pin 13 (derniere sortie inverseur, entree cascade) |
|
||||
| `TC4584BF_diodes_cascade_C7_chip_side_p1.jpg` | Cote chip de C7, signal 76 kHz |
|
||||
| `TC4584BF_diodes_cascade_C7_diode_side_p1.jpg` | Cote diode de C7, signal AC couple |
|
||||
| `TC4584BF_diodes_cascade_D6_anode_p1.jpg` | Anode D6 avant inversion |
|
||||
| `TC4584BF_diodes_cascade_D6_cathode_p1.jpg` | Cathode D6 avant inversion |
|
||||
| `TC4584BF_diodes_cascade_D6_cathode_p2.jpg` | Cathode D6 apres inversion — 24V+ |
|
||||
|
||||
---
|
||||
|
||||
## 8. Lecons apprises
|
||||
|
||||
1. **Toujours verifier la disposition visuelle (+)/(-) d'un symbole d'op-amp telecharge** — le symbole SnapEDA OPA1642 a (+) en bas et (-) en haut, a l'inverse de la convention. C'est la source des 3 erreurs du preamp.
|
||||
2. **L'impedance du multimetre (10 MOhm) trompe les mesures derriere 1 GOhm** — POL affiche 0V ou 5V alors qu'il y a 25V reels. Seul le test fonctionnel (audio) est fiable.
|
||||
3. **La cage de Faraday est indispensable** — sans le corps metallique, le 50 Hz noie completement le signal. Sur un circuit haute impedance (1 GOhm), le blindage n'est pas optionnel.
|
||||
4. **Le montage mecanique peut etre l'etape la plus importante** — 2 jours de debug circuit, et c'est le montage dans le boitier qui a tout resolu.
|
||||
5. **Cross-tester avec un micro commercial** (Vibe C1) a ete crucial pour isoler les problemes (capsule ? preamp ? hex inverter ?).
|
||||
|
||||
---
|
||||
|
||||
## Voir aussi
|
||||
|
||||
- [[02_PRODUITS_PHYSIQUES/Microphone/Conception/CORRECTIONS_PCB_P2]] — Liste des corrections pour les prochains PCBs
|
||||
- [[02_PRODUITS_PHYSIQUES/Microphone/Conception/RAPPORT_BUG_PREAMP_P1.pdf]] — Rapport detaille des 3 erreurs du schema preamp
|
||||
- [[02_PRODUITS_PHYSIQUES/Microphone/Conception/GUIDE_DEBUG_TALAS_ONE]] — Procedure de debug
|
||||
- [[02_PRODUITS_PHYSIQUES/Microphone/Conception/CABLAGE_INTER_CARTES_TALAS_ONE]] — Schema de cablage
|
||||
BIN
02_PRODUITS_PHYSIQUES/Microphone/Conception/K87+Saddle.stl
Normal file
BIN
02_PRODUITS_PHYSIQUES/Microphone/Conception/K87+Saddle.stl
Normal file
Binary file not shown.
Binary file not shown.
|
|
@ -83,6 +83,9 @@ Le Talas Lite utilise une architecture plus simple (preampli THAT1512, sortie US
|
|||
|
||||
| Document | Description |
|
||||
|----------|-------------|
|
||||
| [[02_PRODUITS_PHYSIQUES/Microphone/Conception/ETAT_PROTOTYPE_P1]] | **Etat complet du premier prototype fonctionnel (12 avril 2026)** : bodges realises, mesures, capsule, cablage, lecons apprises. Document de reference pour comprendre l'etat exact du proto. |
|
||||
| [[02_PRODUITS_PHYSIQUES/Microphone/Conception/CORRECTIONS_PCB_P2]] | **Liste exhaustive des corrections** pour les prochains PCBs (preamp p3 + hex inverter p2) : bugs critiques, ameliorations, procedure KiCad, composants a commander. |
|
||||
| [[02_PRODUITS_PHYSIQUES/Microphone/Conception/RAPPORT_BUG_PREAMP_P1.pdf]] | Analyse topologique detaillee des 3 erreurs de cablage du preamp p1 (confusion pin 2/pin 3 du symbole SnapEDA OPA1642). 10 pages avec netlist, schemas, et options de correction. |
|
||||
| [[02_PRODUITS_PHYSIQUES/Microphone/Conception/CABLAGE_INTER_CARTES_TALAS_ONE]] | Schema complet des 13 fils entre les deux PCBs, le connecteur XLR 5-pin et la capsule. Tableau de cablage, disposition des pads, cable breakout, precautions. |
|
||||
| [[02_PRODUITS_PHYSIQUES/Microphone/Conception/GUIDE_DEBUG_TALAS_ONE]] | Procedure de debug pas a pas : inspection visuelle, tests courts-circuits, test hex inverter en isolation (LDO, oscillateur, POL, ripple), test preampli avec phantom, test systeme complet. Tensions attendues et 8 causes de panne les plus frequentes. |
|
||||
| [[02_PRODUITS_PHYSIQUES/Microphone/Conception/VERIFICATION_SCHEMA_TALAS_ONE]] | Verification composant par composant du schema KiCAD contre la reference AliceOPA. 20 resistances, 14 condensateurs, 2 zeners, 2 OPA1642 -- tout correspond. 5 points d'attention pour le debug a l'atelier. |
|
||||
|
|
@ -93,6 +96,8 @@ Le Talas Lite utilise une architecture plus simple (preampli THAT1512, sortie US
|
|||
|
||||
| Je veux... | Aller vers |
|
||||
|------------|-----------|
|
||||
| Voir l'etat exact du prototype fonctionnel P1 | [[02_PRODUITS_PHYSIQUES/Microphone/Conception/ETAT_PROTOTYPE_P1]] |
|
||||
| Savoir quoi corriger pour les prochains PCBs | [[02_PRODUITS_PHYSIQUES/Microphone/Conception/CORRECTIONS_PCB_P2]] |
|
||||
| Comprendre le cablage entre les cartes et le XLR | [[02_PRODUITS_PHYSIQUES/Microphone/Conception/CABLAGE_INTER_CARTES_TALAS_ONE]] |
|
||||
| Debugger un prototype qui ne produit pas de son | [[02_PRODUITS_PHYSIQUES/Microphone/Conception/GUIDE_DEBUG_TALAS_ONE]] |
|
||||
| Verifier les valeurs des composants sur le schema | [[02_PRODUITS_PHYSIQUES/Microphone/Conception/VERIFICATION_SCHEMA_TALAS_ONE]] |
|
||||
|
|
|
|||
Binary file not shown.
|
After Width: | Height: | Size: 61 KiB |
391
02_PRODUITS_PHYSIQUES/Microphone/Conception/generate_p2.py
Normal file
391
02_PRODUITS_PHYSIQUES/Microphone/Conception/generate_p2.py
Normal file
|
|
@ -0,0 +1,391 @@
|
|||
#!/usr/bin/env python3
|
||||
"""
|
||||
Generate mic_hex_inverter_pcb_prototype_p2 from p1.
|
||||
Adds wiring to the existing components based on AliceOPA reference schematic.
|
||||
|
||||
Convention verified: pin (at x y) IS the wire connection point.
|
||||
Absolute pin position = symbol_position + pin_relative_offset.
|
||||
"""
|
||||
|
||||
import os
|
||||
import re
|
||||
import shutil
|
||||
import uuid
|
||||
import math
|
||||
from copy import deepcopy
|
||||
|
||||
BASE = "/home/senke/Documents/TG__Talas_Group/02_PRODUITS_PHYSIQUES/Microphone/Conception"
|
||||
|
||||
|
||||
def uid():
|
||||
return str(uuid.uuid4())
|
||||
|
||||
|
||||
# IC1 TC4584BF at (95.25, 76.2)
|
||||
# Pin positions (absolute) = symbol_pos + pin_offset
|
||||
IC1_X, IC1_Y = 95.25, 76.2
|
||||
IC1_PINS = {
|
||||
1: (IC1_X + 0.0, IC1_Y + 0.0), # 1A - Gate A input
|
||||
2: (IC1_X + 0.0, IC1_Y - 2.54), # 1Y - Gate A output
|
||||
3: (IC1_X + 0.0, IC1_Y - 5.08), # 2A - Gate B input
|
||||
4: (IC1_X + 0.0, IC1_Y - 7.62), # 2Y - Gate B output
|
||||
5: (IC1_X + 0.0, IC1_Y - 10.16), # 3A - Gate C input
|
||||
6: (IC1_X + 0.0, IC1_Y - 12.7), # 3Y - Gate C output
|
||||
7: (IC1_X + 0.0, IC1_Y - 15.24), # GND
|
||||
8: (IC1_X + 25.4, IC1_Y - 15.24), # 4Y - Gate D output
|
||||
9: (IC1_X + 25.4, IC1_Y - 12.7), # 4A - Gate D input
|
||||
10: (IC1_X + 25.4, IC1_Y - 10.16), # 5A - Gate E input
|
||||
11: (IC1_X + 25.4, IC1_Y - 7.62), # 5Y - Gate E output
|
||||
12: (IC1_X + 25.4, IC1_Y - 5.08), # 6A - Gate F input
|
||||
13: (IC1_X + 25.4, IC1_Y - 2.54), # 6Y - Gate F output
|
||||
14: (IC1_X + 25.4, IC1_Y + 0.0), # VDD
|
||||
}
|
||||
|
||||
# Other components from p1 (pin 1 and pin 2 absolute positions)
|
||||
# C1 (1nF, oscillator timing) at (45.72, 77.47): pin1=(45.72,77.47), pin2=(58.42,77.47)
|
||||
C1_P1 = (45.72, 77.47)
|
||||
C1_P2 = (45.72 + 12.7, 77.47) # K102J20C0GH5TH5 has pin2 at offset (12.7, 0)
|
||||
|
||||
# R3 (10k, oscillator feedback) at (67.31, 57.15): pin1=(67.31,57.15), pin2=(85.09,57.15)
|
||||
R3_P1 = (67.31, 57.15)
|
||||
R3_P2 = (67.31 + 17.78, 57.15) # MFS1_4DCT52A1002F pin2 at offset (17.78, 0)
|
||||
|
||||
# C3 (100nF, decoupling) at (90.17, 121.92): pin1=(90.17,121.92), pin2=(102.87,121.92)
|
||||
C3_P1 = (90.17, 121.92)
|
||||
C3_P2 = (90.17 + 12.7, 121.92)
|
||||
|
||||
# C5 (4.7uF electrolytic) at (80.01, 106.68): pin1=(80.01,106.68), pin2=(92.71,106.68)
|
||||
C5_P1 = (80.01, 106.68)
|
||||
C5_P2 = (80.01 + 12.7, 106.68)
|
||||
|
||||
# R1 (resistor) at (77.47, 66.04): pin1=(77.47,66.04), pin2=(95.25,66.04)
|
||||
R1_P1 = (77.47, 66.04)
|
||||
R1_P2 = (77.47 + 17.78, 66.04) # RGP0207CHK1G0 pin2 at offset (17.78, 0)
|
||||
|
||||
# D2 (1N4148) at (59.69, 93.98): pin1=(59.69,93.98), pin2=(74.93,93.98)
|
||||
D2_P1 = (59.69, 93.98)
|
||||
D2_P2 = (59.69 + 15.24, 93.98) # 1N4148 pin2 at offset (15.24, 0)
|
||||
|
||||
# GND at (130.81, 100.33): pin1=(130.81,100.33)
|
||||
GND1 = (130.81, 100.33)
|
||||
# GNDREF at (160.02, 104.14): pin1=(160.02,104.14)
|
||||
GNDREF = (160.02, 104.14)
|
||||
|
||||
|
||||
def make_wire(x1, y1, x2, y2):
|
||||
"""Generate a KiCAD wire S-expression."""
|
||||
return f""" (wire (pts (xy {x1} {y1}) (xy {x2} {y2}))
|
||||
(stroke (width 0) (type default))
|
||||
(uuid {uid()})
|
||||
)
|
||||
"""
|
||||
|
||||
|
||||
def make_junction(x, y):
|
||||
"""Generate a junction marker."""
|
||||
return f""" (junction (at {x} {y}) (diameter 0) (color 0 0 0 0)
|
||||
(uuid {uid()})
|
||||
)
|
||||
"""
|
||||
|
||||
|
||||
def make_label(text, x, y, angle=0):
|
||||
"""Generate a net label."""
|
||||
return f""" (label "{text}" (at {x} {y} {angle}) (fields_autoplaced)
|
||||
(effects (font (size 1.27 1.27)) (justify left bottom))
|
||||
(uuid {uid()})
|
||||
)
|
||||
"""
|
||||
|
||||
|
||||
def make_no_connect(x, y):
|
||||
"""Generate a no-connect marker."""
|
||||
return f""" (no_connect (at {x} {y}) (uuid {uid()}))
|
||||
"""
|
||||
|
||||
|
||||
def generate_hex_inverter_p2():
|
||||
"""
|
||||
Generate hex inverter p2 by copying p1 and adding wires.
|
||||
|
||||
AliceOPA reference circuit:
|
||||
- Gate F (12→13): oscillator with R3(10k) feedback + C9(1nF) to GND
|
||||
- Charge pump: all 6 gate outputs drive coupling caps to a Cockcroft-Walton diode chain
|
||||
- Gates connected in series: F→E→D→A→B→C (each output feeds next input)
|
||||
- D7→D6→D5→D4→D3→D2→D1 diode chain for voltage multiplication
|
||||
- Output through dual RC filter: R2(1M)+C2(0.1u) → R1(1M)+C1(0.1u) → POL
|
||||
|
||||
The p1 only has 7 real components + 2 power symbols, all UNWIRED.
|
||||
We have: IC1, C1(1nF), R3(10k), C3(100nF), C5(4.7uF), R1, D2(1N4148)
|
||||
|
||||
With only these components, we can wire:
|
||||
1. IC1 pin 14 (VDD) → VDD power rail
|
||||
2. IC1 pin 7 (GND) → GND
|
||||
3. C3 (100nF decoupling) between VDD and GND
|
||||
4. Gate F oscillator: R3 from pin 13 to pin 12, C1 from pin 12 to GND
|
||||
5. Gate F→E→D→A→B→C: chain inputs to outputs
|
||||
6. D2 and C5 at the output stage
|
||||
7. R1 as part of the output filter
|
||||
|
||||
Missing components (user must add in KiCAD):
|
||||
- D1,D3,D4,D5,D6,D7 (6 more 1N4148 diodes for charge pump)
|
||||
- C2,C4,C6,C7,C8 (5 more 0.01uF coupling caps)
|
||||
- R2 (1M output filter resistor)
|
||||
- C2 (0.1uF output filter cap)
|
||||
- U1 MC33761 LDO (optional, for regulated supply)
|
||||
- D8 (protection diode)
|
||||
"""
|
||||
|
||||
p1_dir = os.path.join(BASE, "mic_hex_inverter_pcb_prototype_p1")
|
||||
p2_dir = os.path.join(BASE, "mic_hex_inverter_pcb_prototype_p2")
|
||||
|
||||
# Clean and recreate
|
||||
if os.path.exists(p2_dir):
|
||||
shutil.rmtree(p2_dir)
|
||||
os.makedirs(p2_dir)
|
||||
|
||||
# Copy all p1 files to p2
|
||||
for fname in os.listdir(p1_dir):
|
||||
if fname.startswith('.') or fname.endswith('.lck') or fname == '_autosave-' or 'backups' in fname:
|
||||
continue
|
||||
src = os.path.join(p1_dir, fname)
|
||||
if os.path.isfile(src):
|
||||
new_name = fname.replace('prototype_p1', 'prototype_p2')
|
||||
dst = os.path.join(p2_dir, new_name)
|
||||
with open(src, 'r', errors='replace') as f:
|
||||
content = f.read()
|
||||
content = content.replace('mic_hex_inverter_pcb_prototype_p1', 'mic_hex_inverter_pcb_prototype_p2')
|
||||
with open(dst, 'w') as f:
|
||||
f.write(content)
|
||||
|
||||
# Now add wires to the schematic
|
||||
sch_path = os.path.join(p2_dir, "mic_hex_inverter_pcb_prototype_p2.kicad_sch")
|
||||
with open(sch_path, 'r') as f:
|
||||
content = f.read()
|
||||
|
||||
# Build wire block
|
||||
wires = []
|
||||
|
||||
# === 1. VDD rail ===
|
||||
# IC1 pin 14 (VDD) at (120.65, 76.2) — connect to VDD rail
|
||||
# C3 pin 1 at (90.17, 121.92) — decoupling to VDD
|
||||
# We'll create a VDD bus wire along the top
|
||||
wires.append(make_label("VDD", 120.65, 76.2 - 2.54))
|
||||
wires.append(make_wire(120.65, 76.2, 120.65, 76.2 - 2.54))
|
||||
|
||||
# === 2. GND rail ===
|
||||
# IC1 pin 7 (GND) at (95.25, 60.96)
|
||||
wires.append(make_label("GND", 95.25, 60.96 + 2.54))
|
||||
wires.append(make_wire(95.25, 60.96, 95.25, 60.96 + 2.54))
|
||||
|
||||
# C3 decoupling: pin1 to VDD label, pin2 to GND label
|
||||
wires.append(make_label("VDD", C3_P1[0] - 2.54, C3_P1[1]))
|
||||
wires.append(make_wire(C3_P1[0], C3_P1[1], C3_P1[0] - 2.54, C3_P1[1]))
|
||||
wires.append(make_label("GND", C3_P2[0] + 2.54, C3_P2[1]))
|
||||
wires.append(make_wire(C3_P2[0], C3_P2[1], C3_P2[0] + 2.54, C3_P2[1]))
|
||||
|
||||
# === 3. Oscillator: Gate F ===
|
||||
# R3 feedback: pin1 → IC1 pin 12 (gate F input), pin2 → IC1 pin 13 (gate F output)
|
||||
# R3 at (67.31, 57.15): pin1=(67.31,57.15), pin2=(85.09,57.15)
|
||||
# IC1 pin 12 at (120.65, 71.12)
|
||||
# IC1 pin 13 at (120.65, 73.66)
|
||||
|
||||
# R3 pin2 (85.09, 57.15) → route to IC1 pin 13 (120.65, 73.66)
|
||||
wires.append(make_wire(R3_P2[0], R3_P2[1], 130.0, R3_P2[1])) # right from R3
|
||||
wires.append(make_wire(130.0, R3_P2[1], 130.0, IC1_PINS[13][1])) # down to pin 13 level
|
||||
wires.append(make_wire(130.0, IC1_PINS[13][1], IC1_PINS[13][0], IC1_PINS[13][1])) # left to pin 13
|
||||
|
||||
# R3 pin1 (67.31, 57.15) → route to IC1 pin 12 (120.65, 71.12)
|
||||
wires.append(make_wire(R3_P1[0], R3_P1[1], R3_P1[0], IC1_PINS[12][1])) # down to pin 12 level
|
||||
wires.append(make_wire(R3_P1[0], IC1_PINS[12][1], IC1_PINS[12][0], IC1_PINS[12][1])) # right to pin 12
|
||||
|
||||
# C1 (1nF oscillator timing): pin1 → IC1 pin 12 node, pin2 → GND
|
||||
# C1 at (45.72, 77.47): pin1=(45.72,77.47), pin2=(58.42,77.47)
|
||||
# Connect C1 pin2 to the wire going to pin 12 (at y=71.12)
|
||||
wires.append(make_wire(C1_P2[0], C1_P2[1], C1_P2[0], IC1_PINS[12][1])) # up from C1
|
||||
wires.append(make_wire(C1_P2[0], IC1_PINS[12][1], R3_P1[0], IC1_PINS[12][1])) # right to R3-pin12 node
|
||||
wires.append(make_junction(R3_P1[0], IC1_PINS[12][1]))
|
||||
# C1 pin1 to GND
|
||||
wires.append(make_label("GND", C1_P1[0] - 2.54, C1_P1[1]))
|
||||
wires.append(make_wire(C1_P1[0], C1_P1[1], C1_P1[0] - 2.54, C1_P1[1]))
|
||||
|
||||
# === 4. Gate chain: F→E→D→A→B→C ===
|
||||
# In the AliceOPA, all gate inputs are driven by the oscillator (gate F output)
|
||||
# Gate F output (pin 13) feeds ALL other gate inputs
|
||||
|
||||
# Connect IC1 pin 13 (gate F output) to all other inputs via a bus
|
||||
osc_node_x = 130.0
|
||||
osc_node_y = IC1_PINS[13][1] # 73.66
|
||||
|
||||
# Already have wire from R3_P2 to pin 13 via (130, 73.66)
|
||||
# Now branch from pin 13 to other inputs
|
||||
|
||||
# Gate E input: pin 10 at (120.65, 66.04) - on right side
|
||||
wires.append(make_wire(130.0, osc_node_y, 130.0, IC1_PINS[10][1]))
|
||||
wires.append(make_wire(130.0, IC1_PINS[10][1], IC1_PINS[10][0], IC1_PINS[10][1]))
|
||||
wires.append(make_junction(130.0, osc_node_y))
|
||||
|
||||
# Gate D input: pin 9 at (120.65, 63.5) - on right side
|
||||
wires.append(make_wire(130.0, IC1_PINS[10][1], 130.0, IC1_PINS[9][1]))
|
||||
wires.append(make_wire(130.0, IC1_PINS[9][1], IC1_PINS[9][0], IC1_PINS[9][1]))
|
||||
wires.append(make_junction(130.0, IC1_PINS[10][1]))
|
||||
|
||||
# Gate A input: pin 1 at (95.25, 76.2) - on left side
|
||||
# Need to route around the IC
|
||||
wires.append(make_wire(130.0, IC1_PINS[9][1], 130.0, 55.0)) # extend up past IC
|
||||
wires.append(make_wire(130.0, 55.0, 85.0, 55.0)) # go left above IC
|
||||
wires.append(make_wire(85.0, 55.0, 85.0, IC1_PINS[1][1])) # down to pin 1 level
|
||||
wires.append(make_wire(85.0, IC1_PINS[1][1], IC1_PINS[1][0], IC1_PINS[1][1])) # right to pin 1
|
||||
wires.append(make_junction(130.0, IC1_PINS[9][1]))
|
||||
|
||||
# Gate B input: pin 3 at (95.25, 71.12) - left side
|
||||
wires.append(make_wire(85.0, IC1_PINS[1][1], 85.0, IC1_PINS[3][1]))
|
||||
wires.append(make_wire(85.0, IC1_PINS[3][1], IC1_PINS[3][0], IC1_PINS[3][1]))
|
||||
wires.append(make_junction(85.0, IC1_PINS[1][1]))
|
||||
|
||||
# Gate C input: pin 5 at (95.25, 66.04) - left side
|
||||
wires.append(make_wire(85.0, IC1_PINS[3][1], 85.0, IC1_PINS[5][1]))
|
||||
wires.append(make_wire(85.0, IC1_PINS[5][1], IC1_PINS[5][0], IC1_PINS[5][1]))
|
||||
wires.append(make_junction(85.0, IC1_PINS[3][1]))
|
||||
|
||||
# === 5. Output stage ===
|
||||
# Gate outputs labeled for connection to charge pump caps (user adds caps+diodes)
|
||||
# Label each gate output for easy identification
|
||||
|
||||
# Gate A output (pin 2) at (95.25, 73.66)
|
||||
wires.append(make_label("GA_OUT", IC1_PINS[2][0] - 10, IC1_PINS[2][1]))
|
||||
wires.append(make_wire(IC1_PINS[2][0], IC1_PINS[2][1], IC1_PINS[2][0] - 10, IC1_PINS[2][1]))
|
||||
|
||||
# Gate B output (pin 4) at (95.25, 68.58)
|
||||
wires.append(make_label("GB_OUT", IC1_PINS[4][0] - 10, IC1_PINS[4][1]))
|
||||
wires.append(make_wire(IC1_PINS[4][0], IC1_PINS[4][1], IC1_PINS[4][0] - 10, IC1_PINS[4][1]))
|
||||
|
||||
# Gate C output (pin 6) at (95.25, 63.5)
|
||||
wires.append(make_label("GC_OUT", IC1_PINS[6][0] - 10, IC1_PINS[6][1]))
|
||||
wires.append(make_wire(IC1_PINS[6][0], IC1_PINS[6][1], IC1_PINS[6][0] - 10, IC1_PINS[6][1]))
|
||||
|
||||
# Gate D output (pin 8) at (120.65, 60.96)
|
||||
wires.append(make_label("GD_OUT", IC1_PINS[8][0] + 5, IC1_PINS[8][1]))
|
||||
wires.append(make_wire(IC1_PINS[8][0], IC1_PINS[8][1], IC1_PINS[8][0] + 5, IC1_PINS[8][1]))
|
||||
|
||||
# Gate E output (pin 11) at (120.65, 68.58)
|
||||
wires.append(make_label("GE_OUT", IC1_PINS[11][0] + 5, IC1_PINS[11][1]))
|
||||
wires.append(make_wire(IC1_PINS[11][0], IC1_PINS[11][1], IC1_PINS[11][0] + 5, IC1_PINS[11][1]))
|
||||
|
||||
# Gate F output already connected to oscillator feedback
|
||||
|
||||
# === 6. Wire existing D2 and output components ===
|
||||
# D2 (1N4148) at (59.69, 93.98) — part of charge pump, connect to output node
|
||||
# Label it for the charge pump chain
|
||||
wires.append(make_label("PUMP", D2_P1[0] - 3, D2_P1[1]))
|
||||
wires.append(make_wire(D2_P1[0], D2_P1[1], D2_P1[0] - 3, D2_P1[1]))
|
||||
wires.append(make_label("HV_OUT", D2_P2[0] + 3, D2_P2[1]))
|
||||
wires.append(make_wire(D2_P2[0], D2_P2[1], D2_P2[0] + 3, D2_P2[1]))
|
||||
|
||||
# C5 (4.7uF) output filter: pin1 to HV_OUT, pin2 to GND
|
||||
wires.append(make_label("HV_OUT", C5_P1[0] - 3, C5_P1[1]))
|
||||
wires.append(make_wire(C5_P1[0], C5_P1[1], C5_P1[0] - 3, C5_P1[1]))
|
||||
wires.append(make_label("GND", C5_P2[0] + 3, C5_P2[1]))
|
||||
wires.append(make_wire(C5_P2[0], C5_P2[1], C5_P2[0] + 3, C5_P2[1]))
|
||||
|
||||
# R1 output bleeder: pin1 to HV_OUT, pin2 connects to IC1 pin 5 (already wired above)
|
||||
wires.append(make_label("HV_OUT", R1_P1[0] - 3, R1_P1[1]))
|
||||
wires.append(make_wire(R1_P1[0], R1_P1[1], R1_P1[0] - 3, R1_P1[1]))
|
||||
|
||||
# Connect existing GND power symbols
|
||||
wires.append(make_label("GND", GND1[0], GND1[1]))
|
||||
wires.append(make_label("GND", GNDREF[0], GNDREF[1]))
|
||||
|
||||
# === 7. Text annotations ===
|
||||
annotations = f"""
|
||||
(text "OSCILLATEUR\\nGate F: R3(10k) + C1(1nF)\\nFeedback: pin13 → R3 → pin12\\nTiming: pin12 → C1 → GND" (at 45.0 50.0 0)
|
||||
(effects (font (size 1.5 1.5)) (justify left bottom))
|
||||
(uuid {uid()})
|
||||
)
|
||||
(text "POMPE DE CHARGE\\nManque: D1,D3-D7 (1N4148)\\n+ C2,C4,C6-C8 (0.01uF)\\nTopologie Cockcroft-Walton\\nVoir AliceOPA hex_inverter_DC-DC_schematic.pdf" (at 45.0 88.0 0)
|
||||
(effects (font (size 1.5 1.5)) (justify left bottom))
|
||||
(uuid {uid()})
|
||||
)
|
||||
(text "SORTIE HV (~60-80V)\\nD2→C5(4.7uF)→R1\\nManque: R2(1M), C2(0.1uF)\\nDouble filtre RC pour POL" (at 55.0 100.0 0)
|
||||
(effects (font (size 1.5 1.5)) (justify left bottom))
|
||||
(uuid {uid()})
|
||||
)
|
||||
(text "COMPOSANTS MANQUANTS (à ajouter dans KiCAD):\\n- 6x 1N4148 (D1,D3,D4,D5,D6,D7)\\n- 5x 0.01uF (C4,C6,C7,C8 + C12)\\n- 2x 0.1uF (output RC filter)\\n- 1x 1M resistor (R2)\\n- 1x MC33761 LDO (optionnel)\\n- 1x 1uF (C11, LDO input)" (at 140.0 85.0 0)
|
||||
(effects (font (size 1.5 1.5)) (justify left bottom))
|
||||
(uuid {uid()})
|
||||
)
|
||||
"""
|
||||
|
||||
# Insert wires before the closing )
|
||||
wire_block = "\n".join(wires) + annotations
|
||||
content = content.rstrip()
|
||||
if content.endswith(')'):
|
||||
content = content[:-1] + "\n" + wire_block + "\n)\n"
|
||||
|
||||
with open(sch_path, 'w') as f:
|
||||
f.write(content)
|
||||
|
||||
print(f"Hex inverter P2: added {len(wires)} wires/labels/junctions")
|
||||
return p2_dir
|
||||
|
||||
|
||||
def generate_preamp_p2():
|
||||
"""Copy preamp p1 to p2 (schematic already complete with 161 wires)."""
|
||||
p1_dir = os.path.join(BASE, "mic_preamp_pcb_prototype_p1")
|
||||
p2_dir = os.path.join(BASE, "mic_preamp_pcb_prototype_p2")
|
||||
|
||||
if os.path.exists(p2_dir):
|
||||
shutil.rmtree(p2_dir)
|
||||
os.makedirs(p2_dir)
|
||||
|
||||
for fname in os.listdir(p1_dir):
|
||||
if fname.startswith('.') or fname.endswith('.lck') or 'backups' in fname or fname.startswith('~') or fname.startswith('retro'):
|
||||
continue
|
||||
src = os.path.join(p1_dir, fname)
|
||||
if os.path.isfile(src):
|
||||
new_name = fname.replace('prototype_p1', 'prototype_p2')
|
||||
dst = os.path.join(p2_dir, new_name)
|
||||
with open(src, 'r', errors='replace') as f:
|
||||
content = f.read()
|
||||
content = content.replace('mic_preamp_pcb_prototype_p1', 'mic_preamp_pcb_prototype_p2')
|
||||
with open(dst, 'w') as f:
|
||||
f.write(content)
|
||||
|
||||
print(f"Preamp P2: copied from P1 (schematic already has 72 components + 161 wires)")
|
||||
return p2_dir
|
||||
|
||||
|
||||
if __name__ == '__main__':
|
||||
print("=" * 60)
|
||||
print("Generating Talas Microphone PCB Prototype P2 projects")
|
||||
print("Based on AliceOPA reference schematics")
|
||||
print("=" * 60)
|
||||
|
||||
print("\n--- Hex Inverter P2 ---")
|
||||
hex_dir = generate_hex_inverter_p2()
|
||||
|
||||
print("\n--- Preamp OPA P2 ---")
|
||||
preamp_dir = generate_preamp_p2()
|
||||
|
||||
# Copy Library.pretty for preamp if it exists
|
||||
lib_src = os.path.join(BASE, "mic_preamp_pcb_prototype_p1/Library.pretty")
|
||||
lib_dst = os.path.join(preamp_dir, "Library.pretty")
|
||||
if os.path.isdir(lib_src) and not os.path.exists(lib_dst):
|
||||
shutil.copytree(lib_src, lib_dst)
|
||||
print("Copied Library.pretty for preamp P2")
|
||||
|
||||
fp_src = os.path.join(BASE, "mic_preamp_pcb_prototype_p1/fp-lib-table")
|
||||
fp_dst = os.path.join(preamp_dir, "fp-lib-table")
|
||||
if os.path.isfile(fp_src) and not os.path.exists(fp_dst):
|
||||
shutil.copy2(fp_src, fp_dst)
|
||||
|
||||
print("\n" + "=" * 60)
|
||||
print("Done!")
|
||||
print(f" Hex inverter: {hex_dir}")
|
||||
print(f" Preamp OPA: {preamp_dir}")
|
||||
print("\nNext steps:")
|
||||
print(" 1. Open each .kicad_pro in KiCAD")
|
||||
print(" 2. Hex inverter: add missing components (see annotations on schematic)")
|
||||
print(" 3. Run ERC on both schematics")
|
||||
print(" 4. Update PCB from schematic, then route")
|
||||
print("=" * 60)
|
||||
|
|
@ -0,0 +1,214 @@
|
|||
ERC report (2026-04-10T00:15:07+0200, Encoding UTF8)
|
||||
Report includes: Errors, Warnings
|
||||
|
||||
***** Sheet /
|
||||
[label_dangling]: Label not connected to anything
|
||||
; error
|
||||
@(85.25 mm, 68.58 mm): Label 'GB_OUT'
|
||||
[label_dangling]: Label not connected to anything
|
||||
; error
|
||||
@(56.69 mm, 93.98 mm): Label 'PUMP'
|
||||
[label_dangling]: Label not connected to anything
|
||||
; error
|
||||
@(85.25 mm, 73.66 mm): Label 'GA_OUT'
|
||||
[pin_not_connected]: Pin not connected
|
||||
; error
|
||||
@(95.25 mm, 78.74 mm): Symbol IC1 Pin 2 [O1, Passive, Line]
|
||||
[pin_not_connected]: Pin not connected
|
||||
; error
|
||||
@(95.25 mm, 81.28 mm): Symbol IC1 Pin 3 [I2, Passive, Line]
|
||||
[pin_not_connected]: Pin not connected
|
||||
; error
|
||||
@(95.25 mm, 83.82 mm): Symbol IC1 Pin 4 [O2, Passive, Line]
|
||||
[pin_not_connected]: Pin not connected
|
||||
; error
|
||||
@(95.25 mm, 86.36 mm): Symbol IC1 Pin 5 [I3, Passive, Line]
|
||||
[pin_not_connected]: Pin not connected
|
||||
; error
|
||||
@(95.25 mm, 88.90 mm): Symbol IC1 Pin 6 [O3, Passive, Line]
|
||||
[pin_not_connected]: Pin not connected
|
||||
; error
|
||||
@(95.25 mm, 91.44 mm): Symbol IC1 Pin 7 [VSS, Passive, Line]
|
||||
[label_dangling]: Label not connected to anything
|
||||
; error
|
||||
@(125.65 mm, 60.96 mm): Label 'GD_OUT'
|
||||
[label_dangling]: Label not connected to anything
|
||||
; error
|
||||
@(125.65 mm, 68.58 mm): Label 'GE_OUT'
|
||||
[pin_not_connected]: Pin not connected
|
||||
; error
|
||||
@(120.65 mm, 78.74 mm): Symbol IC1 Pin 13 [I6, Passive, Line]
|
||||
[pin_not_connected]: Pin not connected
|
||||
; error
|
||||
@(120.65 mm, 81.28 mm): Symbol IC1 Pin 12 [O6, Passive, Line]
|
||||
[pin_not_connected]: Pin not connected
|
||||
; error
|
||||
@(120.65 mm, 83.82 mm): Symbol IC1 Pin 11 [I5, Passive, Line]
|
||||
[pin_not_connected]: Pin not connected
|
||||
; error
|
||||
@(120.65 mm, 86.36 mm): Symbol IC1 Pin 10 [O5, Passive, Line]
|
||||
[pin_not_connected]: Pin not connected
|
||||
; error
|
||||
@(120.65 mm, 88.90 mm): Symbol IC1 Pin 9 [I4, Passive, Line]
|
||||
[pin_not_connected]: Pin not connected
|
||||
; error
|
||||
@(120.65 mm, 91.44 mm): Symbol IC1 Pin 8 [O4, Passive, Line]
|
||||
[power_pin_not_driven]: Input Power pin not driven by any Output Power pins
|
||||
; error
|
||||
@(130.81 mm, 100.33 mm): Symbol #PWR01 Hidden pin 1 [GND, Power input, Line]
|
||||
[footprint_link_issues]: The current configuration does not include the footprint library ''.
|
||||
; warning
|
||||
@(67.31 mm, 57.15 mm): Symbol R3 [MFS1_4DCT52A1002F]
|
||||
[lib_symbol_issues]: The current configuration does not include the symbol library 'MFS1_4DCT52A1002F'
|
||||
; warning
|
||||
@(67.31 mm, 57.15 mm): Symbol R3 [MFS1_4DCT52A1002F]
|
||||
[footprint_link_issues]: The current configuration does not include the footprint library '1nF'.
|
||||
; warning
|
||||
@(45.72 mm, 77.47 mm): Symbol C1 [K102J20C0GH5TH5]
|
||||
[lib_symbol_issues]: The current configuration does not include the symbol library 'K102J20C0GH5TH5'
|
||||
; warning
|
||||
@(45.72 mm, 77.47 mm): Symbol C1 [K102J20C0GH5TH5]
|
||||
[endpoint_off_grid]: Symbol pin or wire end off connection grid
|
||||
; warning
|
||||
@(77.47 mm, 66.04 mm): Horizontal Wire, length 3.00 mm
|
||||
[endpoint_off_grid]: Symbol pin or wire end off connection grid
|
||||
; warning
|
||||
@(85.00 mm, 55.00 mm): Vertical Wire, length 16.12 mm
|
||||
[footprint_link_issues]: The current configuration does not include the footprint library ''.
|
||||
; warning
|
||||
@(77.47 mm, 66.04 mm): Symbol R1 [RGP0207CHK1G0]
|
||||
[lib_symbol_issues]: The current configuration does not include the symbol library 'RGP0207CHK1G0'
|
||||
; warning
|
||||
@(77.47 mm, 66.04 mm): Symbol R1 [RGP0207CHK1G0]
|
||||
[endpoint_off_grid]: Symbol pin or wire end off connection grid
|
||||
; warning
|
||||
@(95.25 mm, 63.50 mm): Horizontal Wire, length 10.00 mm
|
||||
[endpoint_off_grid]: Symbol pin or wire end off connection grid
|
||||
; warning
|
||||
@(85.00 mm, 66.04 mm): Horizontal Wire, length 10.25 mm
|
||||
[endpoint_off_grid]: Symbol pin or wire end off connection grid
|
||||
; warning
|
||||
@(95.25 mm, 68.58 mm): Horizontal Wire, length 10.00 mm
|
||||
[endpoint_off_grid]: Symbol pin or wire end off connection grid
|
||||
; warning
|
||||
@(59.69 mm, 93.98 mm): Horizontal Wire, length 3.00 mm
|
||||
[endpoint_off_grid]: Symbol pin or wire end off connection grid
|
||||
; warning
|
||||
@(85.00 mm, 71.12 mm): Vertical Wire, length 5.08 mm
|
||||
[endpoint_off_grid]: Symbol pin or wire end off connection grid
|
||||
; warning
|
||||
@(67.31 mm, 71.12 mm): Horizontal Wire, length 17.69 mm
|
||||
[endpoint_off_grid]: Symbol pin or wire end off connection grid
|
||||
; warning
|
||||
@(85.00 mm, 71.12 mm): Horizontal Wire, length 10.25 mm
|
||||
[footprint_link_issues]: The current configuration does not include the footprint library ''.
|
||||
; warning
|
||||
@(59.69 mm, 93.98 mm): Symbol D2 [1N4148]
|
||||
[lib_symbol_issues]: The current configuration does not include the symbol library '1N4148'
|
||||
; warning
|
||||
@(59.69 mm, 93.98 mm): Symbol D2 [1N4148]
|
||||
[endpoint_off_grid]: Symbol pin or wire end off connection grid
|
||||
; warning
|
||||
@(95.25 mm, 73.66 mm): Horizontal Wire, length 10.00 mm
|
||||
[unconnected_wire_endpoint]: Unconnected wire endpoint
|
||||
; warning
|
||||
@(95.25 mm, 60.96 mm): Vertical Wire, length 2.54 mm
|
||||
[endpoint_off_grid]: Symbol pin or wire end off connection grid
|
||||
; warning
|
||||
@(85.00 mm, 76.20 mm): Horizontal Wire, length 10.25 mm
|
||||
[endpoint_off_grid]: Symbol pin or wire end off connection grid
|
||||
; warning
|
||||
@(85.00 mm, 76.20 mm): Vertical Wire, length 5.08 mm
|
||||
[unconnected_wire_endpoint]: Unconnected wire endpoint
|
||||
; warning
|
||||
@(95.25 mm, 68.58 mm): Horizontal Wire, length 10.00 mm
|
||||
[unconnected_wire_endpoint]: Unconnected wire endpoint
|
||||
; warning
|
||||
@(85.00 mm, 71.12 mm): Horizontal Wire, length 10.25 mm
|
||||
[unconnected_wire_endpoint]: Unconnected wire endpoint
|
||||
; warning
|
||||
@(95.25 mm, 73.66 mm): Horizontal Wire, length 10.00 mm
|
||||
[footprint_link_issues]: The current configuration does not include the footprint library ''.
|
||||
; warning
|
||||
@(95.25 mm, 76.20 mm): Symbol IC1 [TC4584BF_EL,N,F_]
|
||||
[lib_symbol_issues]: The current configuration does not include the symbol library 'TC4584BF_EL_N_F_'
|
||||
; warning
|
||||
@(95.25 mm, 76.20 mm): Symbol IC1 [TC4584BF_EL,N,F_]
|
||||
[endpoint_off_grid]: Symbol pin or wire end off connection grid
|
||||
; warning
|
||||
@(74.93 mm, 93.98 mm): Horizontal Wire, length 3.00 mm
|
||||
[endpoint_off_grid]: Symbol pin or wire end off connection grid
|
||||
; warning
|
||||
@(80.01 mm, 106.68 mm): Horizontal Wire, length 3.00 mm
|
||||
[footprint_link_issues]: The current configuration does not include the footprint library ''.
|
||||
; warning
|
||||
@(80.01 mm, 106.68 mm): Symbol C5 [ECE-A1VKS4R7]
|
||||
[lib_symbol_issues]: The current configuration does not include the symbol library 'ECE-A1VKS4R7'
|
||||
; warning
|
||||
@(80.01 mm, 106.68 mm): Symbol C5 [ECE-A1VKS4R7]
|
||||
[unconnected_wire_endpoint]: Unconnected wire endpoint
|
||||
; warning
|
||||
@(120.65 mm, 60.96 mm): Horizontal Wire, length 5.00 mm
|
||||
[unconnected_wire_endpoint]: Unconnected wire endpoint
|
||||
; warning
|
||||
@(130.00 mm, 63.50 mm): Horizontal Wire, length 9.35 mm
|
||||
[unconnected_wire_endpoint]: Unconnected wire endpoint
|
||||
; warning
|
||||
@(130.00 mm, 66.04 mm): Horizontal Wire, length 9.35 mm
|
||||
[unconnected_wire_endpoint]: Unconnected wire endpoint
|
||||
; warning
|
||||
@(120.65 mm, 68.58 mm): Horizontal Wire, length 5.00 mm
|
||||
[endpoint_off_grid]: Symbol pin or wire end off connection grid
|
||||
; warning
|
||||
@(120.65 mm, 60.96 mm): Horizontal Wire, length 5.00 mm
|
||||
[endpoint_off_grid]: Symbol pin or wire end off connection grid
|
||||
; warning
|
||||
@(130.00 mm, 55.00 mm): Horizontal Wire, length 45.00 mm
|
||||
[endpoint_off_grid]: Symbol pin or wire end off connection grid
|
||||
; warning
|
||||
@(130.00 mm, 57.15 mm): Vertical Wire, length 6.35 mm
|
||||
[endpoint_off_grid]: Symbol pin or wire end off connection grid
|
||||
; warning
|
||||
@(85.09 mm, 57.15 mm): Horizontal Wire, length 44.91 mm
|
||||
[endpoint_off_grid]: Symbol pin or wire end off connection grid
|
||||
; warning
|
||||
@(120.65 mm, 68.58 mm): Horizontal Wire, length 5.00 mm
|
||||
[endpoint_off_grid]: Symbol pin or wire end off connection grid
|
||||
; warning
|
||||
@(92.71 mm, 106.68 mm): Horizontal Wire, length 3.00 mm
|
||||
[endpoint_off_grid]: Symbol pin or wire end off connection grid
|
||||
; warning
|
||||
@(130.00 mm, 63.50 mm): Horizontal Wire, length 9.35 mm
|
||||
[endpoint_off_grid]: Symbol pin or wire end off connection grid
|
||||
; warning
|
||||
@(130.00 mm, 63.50 mm): Vertical Wire, length 8.50 mm
|
||||
[endpoint_off_grid]: Symbol pin or wire end off connection grid
|
||||
; warning
|
||||
@(130.00 mm, 66.04 mm): Vertical Wire, length 2.54 mm
|
||||
[endpoint_off_grid]: Symbol pin or wire end off connection grid
|
||||
; warning
|
||||
@(130.00 mm, 66.04 mm): Horizontal Wire, length 9.35 mm
|
||||
[endpoint_off_grid]: Symbol pin or wire end off connection grid
|
||||
; warning
|
||||
@(130.00 mm, 73.66 mm): Vertical Wire, length 7.62 mm
|
||||
[endpoint_off_grid]: Symbol pin or wire end off connection grid
|
||||
; warning
|
||||
@(130.00 mm, 73.66 mm): Horizontal Wire, length 9.35 mm
|
||||
[footprint_link_issues]: The current configuration does not include the footprint library ''.
|
||||
; warning
|
||||
@(90.17 mm, 121.92 mm): Symbol C3 [K104M20X7RH53L2]
|
||||
[lib_symbol_issues]: The current configuration does not include the symbol library 'K104M20X7RH53L2'
|
||||
; warning
|
||||
@(90.17 mm, 121.92 mm): Symbol C3 [K104M20X7RH53L2]
|
||||
[lib_symbol_mismatch]: Symbol 'GND' doesn't match copy in library 'power'
|
||||
; warning
|
||||
@(130.81 mm, 100.33 mm): Symbol #PWR01 [GND]
|
||||
[lib_symbol_mismatch]: Symbol 'GNDREF' doesn't match copy in library 'power'
|
||||
; warning
|
||||
@(160.02 mm, 104.14 mm): Symbol #PWR02 [GNDREF]
|
||||
[multiple_net_names]: Both GND and GNDREF are attached to the same items; GND will be used in the netlist
|
||||
; warning
|
||||
@(130.81 mm, 100.33 mm): Symbol #PWR01 Hidden pin 1 [GND, Power input, Line]
|
||||
@(160.02 mm, 104.14 mm): Symbol #PWR02 Hidden pin 1 [GNDREF, Power input, Line]
|
||||
|
||||
** ERC messages: 69 Errors 18 Warnings 51
|
||||
Binary file not shown.
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,422 @@
|
|||
%PDF-1.4
|
||||
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|
||||
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|
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|
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|
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|
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|
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|
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||||
<<
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||||
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||||
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|
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4 0 obj
|
||||
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|
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|
||||
6 0 obj
|
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>> /Rotate 0 /Trans <<
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|
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7 0 obj
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<<
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>> /Rotate 0 /Trans <<
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8 0 obj
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||||
<<
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|
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9 0 obj
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<<
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10 0 obj
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<<
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>>
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11 0 obj
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<<
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>> /Rotate 0 /Trans <<
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>>
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>>
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|
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12 0 obj
|
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<<
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/Contents 33 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 28 0 R /Resources <<
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>> /Rotate 0 /Trans <<
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>>
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>>
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13 0 obj
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<<
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/Contents 34 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 28 0 R /Resources <<
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/Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ]
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>> /Rotate 0 /Trans <<
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>>
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>>
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14 0 obj
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<<
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/Contents 35 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 28 0 R /Resources <<
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/Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ]
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>> /Rotate 0 /Trans <<
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>>
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>>
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|
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15 0 obj
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<<
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/Contents 36 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 28 0 R /Resources <<
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/Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ]
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>> /Rotate 0 /Trans <<
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16 0 obj
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/Contents 37 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 28 0 R /Resources <<
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/Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ]
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>> /Rotate 0 /Trans <<
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17 0 obj
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/Contents 38 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 28 0 R /Resources <<
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>> /Rotate 0 /Trans <<
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18 0 obj
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>> /Rotate 0 /Trans <<
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19 0 obj
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<<
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>> /Rotate 0 /Trans <<
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>> /Rotate 0 /Trans <<
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21 0 obj
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>> /Rotate 0 /Trans <<
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>>
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>>
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26 0 obj
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27 0 obj
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28 0 obj
|
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|
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>>
|
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|
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29 0 obj
|
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<<
|
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|
||||
>>
|
||||
stream
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|
||||
"default_text_size": 50.0,
|
||||
"field_names": [],
|
||||
"intersheets_ref_own_page": false,
|
||||
"intersheets_ref_prefix": "",
|
||||
"intersheets_ref_short": false,
|
||||
"intersheets_ref_show": false,
|
||||
"intersheets_ref_suffix": "",
|
||||
"junction_size_choice": 3,
|
||||
"label_size_ratio": 0.375,
|
||||
"pin_symbol_size": 25.0,
|
||||
"text_offset_ratio": 0.15
|
||||
},
|
||||
"legacy_lib_dir": "",
|
||||
"legacy_lib_list": [],
|
||||
"meta": {
|
||||
"version": 1
|
||||
},
|
||||
"net_format_name": "",
|
||||
"page_layout_descr_file": "",
|
||||
"plot_directory": "",
|
||||
"spice_current_sheet_as_root": false,
|
||||
"spice_external_command": "spice \"%I\"",
|
||||
"spice_model_current_sheet_as_root": true,
|
||||
"spice_save_all_currents": false,
|
||||
"spice_save_all_voltages": false,
|
||||
"subpart_first_id": 65,
|
||||
"subpart_id_separator": 0
|
||||
},
|
||||
"sheets": [
|
||||
[
|
||||
"3d8e7ae7-5f8e-4bf5-8c8e-786bf8970fd7",
|
||||
""
|
||||
]
|
||||
],
|
||||
"text_variables": {}
|
||||
}
|
||||
File diff suppressed because it is too large
Load diff
File diff suppressed because one or more lines are too long
|
|
@ -0,0 +1,126 @@
|
|||
ERC report (2026-04-10T00:15:08+0200, Encoding UTF8)
|
||||
Report includes: Errors, Warnings
|
||||
|
||||
***** Sheet /
|
||||
[power_pin_not_driven]: Input Power pin not driven by any Output Power pins
|
||||
; error
|
||||
@(50.80 mm, 44.45 mm): Symbol #PWR0102 Hidden pin 1 [Earth, Power input, Line]
|
||||
[power_pin_not_driven]: Input Power pin not driven by any Output Power pins
|
||||
; error
|
||||
@(45.72 mm, 59.69 mm): Symbol IC2 Pin 8 [Power input, Line]
|
||||
[pin_not_connected]: Pin not connected
|
||||
; error
|
||||
@(21.59 mm, 85.09 mm): Symbol J1 Pin 1 [Pin_1, Passive, Line]
|
||||
[power_pin_not_driven]: Input Power pin not driven by any Output Power pins
|
||||
; error
|
||||
@(171.45 mm, 58.42 mm): Symbol IC1 Pin 8 [Power input, Line]
|
||||
[power_pin_not_driven]: Input Power pin not driven by any Output Power pins
|
||||
; error
|
||||
@(171.45 mm, 73.66 mm): Symbol IC1 Pin 4 [Power input, Line]
|
||||
[footprint_link_issues]: The current configuration does not include the footprint library 'C47u35v'.
|
||||
; warning
|
||||
@(50.80 mm, 39.37 mm): Symbol C14 [C_Polarized]
|
||||
[footprint_link_issues]: The current configuration does not include the footprint library 'R1Go'.
|
||||
; warning
|
||||
@(34.29 mm, 54.61 mm): Symbol R20 [R]
|
||||
[lib_symbol_mismatch]: Symbol 'Earth' doesn't match copy in library 'power'
|
||||
; warning
|
||||
@(50.80 mm, 44.45 mm): Symbol #PWR0102 [Earth]
|
||||
[lib_symbol_mismatch]: Symbol 'Earth' doesn't match copy in library 'power'
|
||||
; warning
|
||||
@(57.15 mm, 44.45 mm): Symbol #PWR0103 [Earth]
|
||||
[footprint_link_issues]: The current configuration does not include the footprint library 'opa1642'.
|
||||
; warning
|
||||
@(45.72 mm, 67.31 mm): Symbol IC2 [OPA1642AID]
|
||||
[lib_symbol_issues]: The current configuration does not include the symbol library 'OPA1642AID'
|
||||
; warning
|
||||
@(45.72 mm, 67.31 mm): Symbol IC2 [OPA1642AID]
|
||||
[lib_symbol_mismatch]: Symbol 'GND' doesn't match copy in library 'power'
|
||||
; warning
|
||||
@(64.77 mm, 58.42 mm): Symbol #PWR0104 [GND]
|
||||
[lib_symbol_mismatch]: Symbol 'GND' doesn't match copy in library 'power'
|
||||
; warning
|
||||
@(45.72 mm, 76.20 mm): Symbol #PWR0101 [GND]
|
||||
[footprint_link_issues]: The current configuration does not include the footprint library 'C47u35v'.
|
||||
; warning
|
||||
@(93.98 mm, 53.34 mm): Symbol C12 [C_Polarized]
|
||||
[footprint_link_issues]: The current configuration does not include the footprint library 'C47u63v'.
|
||||
; warning
|
||||
@(99.06 mm, 67.31 mm): Symbol C11 [C_Polarized]
|
||||
[footprint_link_issues]: The current configuration does not include the footprint library 'opa1642'.
|
||||
; warning
|
||||
@(81.28 mm, 91.44 mm): Symbol IC2 [OPA1642AID]
|
||||
[lib_symbol_issues]: The current configuration does not include the symbol library 'OPA1642AID'
|
||||
; warning
|
||||
@(81.28 mm, 91.44 mm): Symbol IC2 [OPA1642AID]
|
||||
[footprint_link_issues]: The current configuration does not include the footprint library 'C47u35v'.
|
||||
; warning
|
||||
@(120.65 mm, 50.80 mm): Symbol C9 [C_Polarized]
|
||||
[lib_symbol_mismatch]: Symbol 'GND' doesn't match copy in library 'power'
|
||||
; warning
|
||||
@(120.65 mm, 55.88 mm): Symbol #PWR0105 [GND]
|
||||
[footprint_link_issues]: The current configuration does not include the footprint library 'C47u63v'.
|
||||
; warning
|
||||
@(99.06 mm, 91.44 mm): Symbol C10 [C_Polarized]
|
||||
[lib_symbol_mismatch]: Symbol 'GND' doesn't match copy in library 'power'
|
||||
; warning
|
||||
@(128.27 mm, 55.88 mm): Symbol #PWR0107 [GND]
|
||||
[lib_symbol_mismatch]: Symbol 'GND' doesn't match copy in library 'power'
|
||||
; warning
|
||||
@(135.89 mm, 55.88 mm): Symbol #PWR0108 [GND]
|
||||
[lib_symbol_mismatch]: Symbol 'GND' doesn't match copy in library 'power'
|
||||
; warning
|
||||
@(124.46 mm, 104.14 mm): Symbol #PWR0106 [GND]
|
||||
[footprint_link_issues]: The current configuration does not include the footprint library 'R1Go'.
|
||||
; warning
|
||||
@(160.02 mm, 53.34 mm): Symbol R10 [R]
|
||||
[footprint_link_issues]: The current configuration does not include the footprint library 'C47u35v'.
|
||||
; warning
|
||||
@(176.53 mm, 38.10 mm): Symbol C7 [C_Polarized]
|
||||
[lib_symbol_mismatch]: Symbol 'Earth' doesn't match copy in library 'power'
|
||||
; warning
|
||||
@(176.53 mm, 43.18 mm): Symbol #PWR0110 [Earth]
|
||||
[footprint_link_issues]: The current configuration does not include the footprint library 'opa1642'.
|
||||
; warning
|
||||
@(171.45 mm, 66.04 mm): Symbol IC1 [OPA1642AID]
|
||||
[lib_symbol_issues]: The current configuration does not include the symbol library 'OPA1642AID'
|
||||
; warning
|
||||
@(171.45 mm, 66.04 mm): Symbol IC1 [OPA1642AID]
|
||||
[footprint_link_issues]: The current configuration does not include the footprint library 'C.022uF50v'.
|
||||
; warning
|
||||
@(182.88 mm, 38.10 mm): Symbol C6 [C]
|
||||
[lib_symbol_mismatch]: Symbol 'GND' doesn't match copy in library 'power'
|
||||
; warning
|
||||
@(171.45 mm, 74.93 mm): Symbol #PWR0109 [GND]
|
||||
[lib_symbol_mismatch]: Symbol 'Earth' doesn't match copy in library 'power'
|
||||
; warning
|
||||
@(182.88 mm, 43.18 mm): Symbol #PWR0111 [Earth]
|
||||
[lib_symbol_mismatch]: Symbol 'GND' doesn't match copy in library 'power'
|
||||
; warning
|
||||
@(190.50 mm, 57.15 mm): Symbol #PWR0112 [GND]
|
||||
[footprint_link_issues]: The current configuration does not include the footprint library 'C47u35v'.
|
||||
; warning
|
||||
@(219.71 mm, 52.07 mm): Symbol C5 [C_Polarized]
|
||||
[footprint_link_issues]: The current configuration does not include the footprint library 'C47u63v'.
|
||||
; warning
|
||||
@(224.79 mm, 66.04 mm): Symbol C4 [C_Polarized]
|
||||
[footprint_link_issues]: The current configuration does not include the footprint library 'C47u63v'.
|
||||
; warning
|
||||
@(224.79 mm, 90.17 mm): Symbol C3 [C_Polarized]
|
||||
[footprint_link_issues]: The current configuration does not include the footprint library 'C47u35v'.
|
||||
; warning
|
||||
@(246.38 mm, 49.53 mm): Symbol C2 [C_Polarized]
|
||||
[lib_symbol_mismatch]: Symbol 'GND' doesn't match copy in library 'power'
|
||||
; warning
|
||||
@(246.38 mm, 54.61 mm): Symbol #PWR0113 [GND]
|
||||
[lib_symbol_mismatch]: Symbol 'GND' doesn't match copy in library 'power'
|
||||
; warning
|
||||
@(254.00 mm, 54.61 mm): Symbol #PWR0115 [GND]
|
||||
[lib_symbol_mismatch]: Symbol 'GND' doesn't match copy in library 'power'
|
||||
; warning
|
||||
@(261.62 mm, 54.61 mm): Symbol #PWR0116 [GND]
|
||||
[lib_symbol_mismatch]: Symbol 'GND' doesn't match copy in library 'power'
|
||||
; warning
|
||||
@(250.19 mm, 102.87 mm): Symbol #PWR0114 [GND]
|
||||
|
||||
** ERC messages: 40 Errors 5 Warnings 35
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
(footprint "conn_holepad" (version 20221018) (generator pcbnew)
|
||||
(layer "F.Cu")
|
||||
(attr through_hole)
|
||||
(fp_text reference "REF**" (at 0 -0.5 unlocked) (layer "F.SilkS")
|
||||
(effects (font (size 1 1) (thickness 0.1)))
|
||||
(tstamp 47113dfe-4d45-4231-91f4-cd0701338629)
|
||||
)
|
||||
(fp_text value "conn_holepad" (at 0 1 unlocked) (layer "F.Fab")
|
||||
(effects (font (size 1 1) (thickness 0.15)))
|
||||
(tstamp 7435b7d9-85bd-495a-b8ab-ac289b127f61)
|
||||
)
|
||||
(fp_text user "${REFERENCE}" (at 0 2.5 unlocked) (layer "F.Fab")
|
||||
(effects (font (size 1 1) (thickness 0.15)))
|
||||
(tstamp 8eee9630-84b7-4aee-8149-af3bd9917f74)
|
||||
)
|
||||
(pad "1" thru_hole circle (at 0 0) (size 3 3) (drill 1.5) (layers "*.Cu" "*.Mask") (tstamp 95b6f2c3-269f-40d9-9ec5-993d6ae92733))
|
||||
)
|
||||
Binary file not shown.
|
|
@ -0,0 +1,8 @@
|
|||
1740346879553
|
||||
Library
|
||||
conn_holepad
|
||||
|
||||
|
||||
0
|
||||
1
|
||||
1
|
||||
|
|
@ -0,0 +1,4 @@
|
|||
(fp_lib_table
|
||||
(version 7)
|
||||
(lib (name "Library")(type "KiCad")(uri "${KIPRJMOD}/Library.pretty")(options "")(descr ""))
|
||||
)
|
||||
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,76 @@
|
|||
{
|
||||
"board": {
|
||||
"active_layer": 34,
|
||||
"active_layer_preset": "",
|
||||
"auto_track_width": true,
|
||||
"hidden_netclasses": [],
|
||||
"hidden_nets": [],
|
||||
"high_contrast_mode": 0,
|
||||
"net_color_mode": 1,
|
||||
"opacity": {
|
||||
"images": 0.6,
|
||||
"pads": 1.0,
|
||||
"tracks": 1.0,
|
||||
"vias": 1.0,
|
||||
"zones": 0.6
|
||||
},
|
||||
"selection_filter": {
|
||||
"dimensions": true,
|
||||
"footprints": true,
|
||||
"graphics": true,
|
||||
"keepouts": true,
|
||||
"lockedItems": false,
|
||||
"otherItems": true,
|
||||
"pads": true,
|
||||
"text": true,
|
||||
"tracks": true,
|
||||
"vias": true,
|
||||
"zones": true
|
||||
},
|
||||
"visible_items": [
|
||||
0,
|
||||
1,
|
||||
2,
|
||||
3,
|
||||
4,
|
||||
5,
|
||||
8,
|
||||
9,
|
||||
10,
|
||||
11,
|
||||
13,
|
||||
15,
|
||||
16,
|
||||
17,
|
||||
18,
|
||||
19,
|
||||
20,
|
||||
21,
|
||||
22,
|
||||
23,
|
||||
24,
|
||||
25,
|
||||
26,
|
||||
27,
|
||||
28,
|
||||
29,
|
||||
30,
|
||||
32,
|
||||
33,
|
||||
34,
|
||||
35,
|
||||
36,
|
||||
39,
|
||||
40
|
||||
],
|
||||
"visible_layers": "fffffff_ffffffff",
|
||||
"zone_display_mode": 0
|
||||
},
|
||||
"meta": {
|
||||
"filename": "mic_preamp_pcb_prototype_p2.kicad_prl",
|
||||
"version": 3
|
||||
},
|
||||
"project": {
|
||||
"files": []
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,490 @@
|
|||
{
|
||||
"board": {
|
||||
"3dviewports": [],
|
||||
"design_settings": {
|
||||
"defaults": {
|
||||
"board_outline_line_width": 0.09999999999999999,
|
||||
"copper_line_width": 0.19999999999999998,
|
||||
"copper_text_italic": false,
|
||||
"copper_text_size_h": 1.5,
|
||||
"copper_text_size_v": 1.5,
|
||||
"copper_text_thickness": 0.3,
|
||||
"copper_text_upright": false,
|
||||
"courtyard_line_width": 0.049999999999999996,
|
||||
"dimension_precision": 4,
|
||||
"dimension_units": 3,
|
||||
"dimensions": {
|
||||
"arrow_length": 1270000,
|
||||
"extension_offset": 500000,
|
||||
"keep_text_aligned": true,
|
||||
"suppress_zeroes": false,
|
||||
"text_position": 0,
|
||||
"units_format": 1
|
||||
},
|
||||
"fab_line_width": 0.09999999999999999,
|
||||
"fab_text_italic": false,
|
||||
"fab_text_size_h": 1.0,
|
||||
"fab_text_size_v": 1.0,
|
||||
"fab_text_thickness": 0.15,
|
||||
"fab_text_upright": false,
|
||||
"other_line_width": 0.15,
|
||||
"other_text_italic": false,
|
||||
"other_text_size_h": 1.0,
|
||||
"other_text_size_v": 1.0,
|
||||
"other_text_thickness": 0.15,
|
||||
"other_text_upright": false,
|
||||
"pads": {
|
||||
"drill": 1.0,
|
||||
"height": 2.0,
|
||||
"width": 2.0
|
||||
},
|
||||
"silk_line_width": 0.15,
|
||||
"silk_text_italic": false,
|
||||
"silk_text_size_h": 1.0,
|
||||
"silk_text_size_v": 1.0,
|
||||
"silk_text_thickness": 0.15,
|
||||
"silk_text_upright": false,
|
||||
"zones": {
|
||||
"min_clearance": 0.5
|
||||
}
|
||||
},
|
||||
"diff_pair_dimensions": [
|
||||
{
|
||||
"gap": 0.0,
|
||||
"via_gap": 0.0,
|
||||
"width": 0.0
|
||||
}
|
||||
],
|
||||
"drc_exclusions": [],
|
||||
"meta": {
|
||||
"version": 2
|
||||
},
|
||||
"rule_severities": {
|
||||
"annular_width": "error",
|
||||
"clearance": "error",
|
||||
"connection_width": "warning",
|
||||
"copper_edge_clearance": "error",
|
||||
"copper_sliver": "warning",
|
||||
"courtyards_overlap": "error",
|
||||
"diff_pair_gap_out_of_range": "error",
|
||||
"diff_pair_uncoupled_length_too_long": "error",
|
||||
"drill_out_of_range": "error",
|
||||
"duplicate_footprints": "warning",
|
||||
"extra_footprint": "warning",
|
||||
"footprint": "error",
|
||||
"footprint_type_mismatch": "ignore",
|
||||
"hole_clearance": "error",
|
||||
"hole_near_hole": "error",
|
||||
"invalid_outline": "error",
|
||||
"isolated_copper": "warning",
|
||||
"item_on_disabled_layer": "error",
|
||||
"items_not_allowed": "error",
|
||||
"length_out_of_range": "error",
|
||||
"lib_footprint_issues": "warning",
|
||||
"lib_footprint_mismatch": "warning",
|
||||
"malformed_courtyard": "error",
|
||||
"microvia_drill_out_of_range": "error",
|
||||
"missing_courtyard": "ignore",
|
||||
"missing_footprint": "warning",
|
||||
"net_conflict": "warning",
|
||||
"npth_inside_courtyard": "ignore",
|
||||
"padstack": "warning",
|
||||
"pth_inside_courtyard": "ignore",
|
||||
"shorting_items": "error",
|
||||
"silk_edge_clearance": "warning",
|
||||
"silk_over_copper": "warning",
|
||||
"silk_overlap": "warning",
|
||||
"skew_out_of_range": "error",
|
||||
"solder_mask_bridge": "error",
|
||||
"starved_thermal": "error",
|
||||
"text_height": "warning",
|
||||
"text_thickness": "warning",
|
||||
"through_hole_pad_without_hole": "error",
|
||||
"too_many_vias": "error",
|
||||
"track_dangling": "warning",
|
||||
"track_width": "error",
|
||||
"tracks_crossing": "error",
|
||||
"unconnected_items": "error",
|
||||
"unresolved_variable": "error",
|
||||
"via_dangling": "warning",
|
||||
"zones_intersect": "error"
|
||||
},
|
||||
"rules": {
|
||||
"max_error": 0.005,
|
||||
"min_clearance": 0.0,
|
||||
"min_connection": 0.0,
|
||||
"min_copper_edge_clearance": 0.0,
|
||||
"min_hole_clearance": 0.25,
|
||||
"min_hole_to_hole": 0.25,
|
||||
"min_microvia_diameter": 0.19999999999999998,
|
||||
"min_microvia_drill": 0.09999999999999999,
|
||||
"min_resolved_spokes": 2,
|
||||
"min_silk_clearance": 0.0,
|
||||
"min_text_height": 0.7999999999999999,
|
||||
"min_text_thickness": 0.08,
|
||||
"min_through_hole_diameter": 0.3,
|
||||
"min_track_width": 0.0,
|
||||
"min_via_annular_width": 0.09999999999999999,
|
||||
"min_via_diameter": 0.5,
|
||||
"solder_mask_clearance": 0.0,
|
||||
"solder_mask_min_width": 0.0,
|
||||
"solder_mask_to_copper_clearance": 0.0,
|
||||
"use_height_for_length_calcs": true
|
||||
},
|
||||
"teardrop_options": [
|
||||
{
|
||||
"td_allow_use_two_tracks": true,
|
||||
"td_curve_segcount": 5,
|
||||
"td_on_pad_in_zone": false,
|
||||
"td_onpadsmd": true,
|
||||
"td_onroundshapesonly": false,
|
||||
"td_ontrackend": false,
|
||||
"td_onviapad": true
|
||||
}
|
||||
],
|
||||
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}
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|
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0.0
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{
|
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|
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|
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}
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|
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},
|
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|
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|
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},
|
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|
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|
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|
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},
|
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|
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|
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]
|
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],
|
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"rule_severities": {
|
||||
"bus_definition_conflict": "error",
|
||||
"bus_entry_needed": "error",
|
||||
"bus_to_bus_conflict": "error",
|
||||
"bus_to_net_conflict": "error",
|
||||
"conflicting_netclasses": "error",
|
||||
"different_unit_footprint": "error",
|
||||
"different_unit_net": "error",
|
||||
"duplicate_reference": "error",
|
||||
"duplicate_sheet_names": "error",
|
||||
"endpoint_off_grid": "warning",
|
||||
"extra_units": "error",
|
||||
"global_label_dangling": "warning",
|
||||
"hier_label_mismatch": "error",
|
||||
"label_dangling": "error",
|
||||
"lib_symbol_issues": "warning",
|
||||
"missing_bidi_pin": "warning",
|
||||
"missing_input_pin": "warning",
|
||||
"missing_power_pin": "error",
|
||||
"missing_unit": "warning",
|
||||
"multiple_net_names": "warning",
|
||||
"net_not_bus_member": "warning",
|
||||
"no_connect_connected": "warning",
|
||||
"no_connect_dangling": "warning",
|
||||
"pin_not_connected": "error",
|
||||
"pin_not_driven": "error",
|
||||
"pin_to_pin": "warning",
|
||||
"power_pin_not_driven": "error",
|
||||
"similar_labels": "warning",
|
||||
"simulation_model_issue": "ignore",
|
||||
"unannotated": "error",
|
||||
"unit_value_mismatch": "error",
|
||||
"unresolved_variable": "error",
|
||||
"wire_dangling": "error"
|
||||
}
|
||||
},
|
||||
"libraries": {
|
||||
"pinned_footprint_libs": [],
|
||||
"pinned_symbol_libs": []
|
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},
|
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"meta": {
|
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"filename": "mic_preamp_pcb_prototype_p2.kicad_pro",
|
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"version": 1
|
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},
|
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|
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"classes": [
|
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{
|
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"bus_width": 12,
|
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"clearance": 0.2,
|
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"diff_pair_gap": 0.25,
|
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"diff_pair_via_gap": 0.25,
|
||||
"diff_pair_width": 0.2,
|
||||
"line_style": 0,
|
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"microvia_diameter": 0.3,
|
||||
"microvia_drill": 0.1,
|
||||
"name": "Default",
|
||||
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
||||
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
||||
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
||||
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|
||||
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|
||||
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|
||||
"gencad": "",
|
||||
"idf": "",
|
||||
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|
||||
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|
||||
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|
||||
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|
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|
||||
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|
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},
|
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|
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|
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|
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"dashed_lines_dash_length_ratio": 12.0,
|
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"dashed_lines_gap_length_ratio": 3.0,
|
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"default_line_thickness": 6.0,
|
||||
"default_text_size": 50.0,
|
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"field_names": [],
|
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"intersheets_ref_own_page": false,
|
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|
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"intersheets_ref_short": false,
|
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"intersheets_ref_show": false,
|
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|
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|
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|
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"pin_symbol_size": 25.0,
|
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"text_offset_ratio": 0.15
|
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},
|
||||
"legacy_lib_dir": "",
|
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"legacy_lib_list": [],
|
||||
"meta": {
|
||||
"version": 1
|
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},
|
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"net_format_name": "",
|
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|
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"plot_directory": "",
|
||||
"spice_current_sheet_as_root": false,
|
||||
"spice_external_command": "spice \"%I\"",
|
||||
"spice_model_current_sheet_as_root": true,
|
||||
"spice_save_all_currents": false,
|
||||
"spice_save_all_voltages": false,
|
||||
"subpart_first_id": 65,
|
||||
"subpart_id_separator": 0
|
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},
|
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"sheets": [
|
||||
[
|
||||
"dde26cd9-6a98-439e-b5e9-17da5761ec2e",
|
||||
""
|
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]
|
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],
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"text_variables": {}
|
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}
|
||||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -26,7 +26,7 @@ Le microphone est le premier produit Talas. Deux gammes partagent le meme ADN :
|
|||
| **Preampli** | OPA1642 (circuit AliceOPA Rev3, double PCB) |
|
||||
| **Connexion** | XLR 5 broches (cable breakout 5->3 fourni) |
|
||||
| **Prix** | 150 EUR TTC |
|
||||
| **Statut** | PCBs concus et commandes, composants en stock, prototype en cours de debug |
|
||||
| **Statut** | **Premier prototype fonctionnel (12 avril 2026)** — canal B, capsule SC600, avec bodges. Refab p3 en preparation |
|
||||
|
||||
---
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,42 @@
|
|||
❯ je viens de tout monter dans le corps du micro et ca fonctionne, plus de buzzer. la prochaines étapes c'est atteindre la meilleure qualité possible mais donc faire des tests audio avec ce protoype. cette
|
||||
session est terminée. /home/senke/Documents/TG__Talas_Group/02_PRODUITS_PHYSIQUES/Microphone/tests/final_first_win_nobridgeD6POL_noparallelcondenser.wav montage en utilisant pol sans bridge entre D6 cathode
|
||||
et pad POL, ni condensateur en parallele entre GND1 et POL.
|
||||
|
||||
● Bravo pour cette victoire ! Le micro fonctionne — capsule SC600 + preamp canal B + hex inverter + corps métallique = signal propre sans buzzer.
|
||||
|
||||
Je sauvegarde l'état actuel du prototype pour la prochaine session.
|
||||
|
||||
Read 1 file, recalled 1 memory, wrote 2 memories (ctrl+o to expand)
|
||||
|
||||
● Etat sauvegardé. Pour la prochaine session, les priorités sont :
|
||||
|
||||
1. Analyser la qualité audio du final_first_win_*.wav — FFT, bruit résiduel, comparaison avec le Vibe C1
|
||||
2. Refab KiCad — corriger le schéma preamp p3 (signal→pin3, feedback pin2→pin1) et hex inverter p2 (routage VCC/GND, orientation D8, augmenter étages CW)
|
||||
3. Remplacer D1 zener (1N4742) pour restaurer le canal A
|
||||
|
||||
Bonne soirée Nikola, belle journée de debug !
|
||||
|
||||
✻ Worked for 43s
|
||||
|
||||
11 tasks (7 done, 4 open)
|
||||
◻ Remplacer D1 zener preamp (claquée)
|
||||
◻ Remonter le Vibe C1 en config originale
|
||||
◻ Refab preamp p3 avec schéma corrigé
|
||||
◻ Réduire pickup 50 Hz sur le montage Talas
|
||||
✔ Corriger wiring capsule dual-diaphragm vs single
|
||||
✔ Valider test audio avec capsule dual single-channel
|
||||
✔ Flipper les 8 diodes du hex inverter
|
||||
✔ Bodge D8 avec fil pour bypass définitif
|
||||
✔ Bodge mid_ctr → mid_right pour connecter VDD au chip
|
||||
✔ Bodge pin 7 TC4584BF → GND
|
||||
… +1 completed
|
||||
|
||||
● How is Claude doing this session? (optional)
|
||||
1: Bad 2: Fine 3: Good 0: Dismiss
|
||||
|
||||
───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
|
||||
❯
|
||||
Resume this session with:──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
|
||||
claude --resume a3acfccb-4203-4d73-bd2b-6946a14d6dcf
|
||||
senke@2a01cb0404747c0055dbef4da700d622:~/Documents/TG__Talas_Group$
|
||||
|
||||
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02_PRODUITS_PHYSIQUES/Microphone/tests/imrpove1_cleaned.wav
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02_PRODUITS_PHYSIQUES/Microphone/tests/test-sc600_n1.wav
Normal file
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02_PRODUITS_PHYSIQUES/Microphone/tests/test-sc600_n1.wav
Normal file
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02_PRODUITS_PHYSIQUES/Microphone/tests/test-sc600_n2.wav
Normal file
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Normal file
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02_PRODUITS_PHYSIQUES/Microphone/tests/test-sc600_n3.wav
Normal file
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02_PRODUITS_PHYSIQUES/Microphone/tests/test-sc600_n3.wav
Normal file
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BIN
02_PRODUITS_PHYSIQUES/Microphone/tests/test-sc600_n4.wav
Normal file
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02_PRODUITS_PHYSIQUES/Microphone/tests/test-sc600_n4.wav
Normal file
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02_PRODUITS_PHYSIQUES/Microphone/tests/test-sc600_n5.wav
Normal file
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02_PRODUITS_PHYSIQUES/Microphone/tests/test-sc600_n5.wav
Normal file
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02_PRODUITS_PHYSIQUES/Microphone/tests/test-sc600_n6.wav
Normal file
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Normal file
Binary file not shown.
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02_PRODUITS_PHYSIQUES/Microphone/tests/test123.wav
Normal file
BIN
02_PRODUITS_PHYSIQUES/Microphone/tests/test123.wav
Normal file
Binary file not shown.
BIN
02_PRODUITS_PHYSIQUES/Microphone/tests/test_final.wav
Normal file
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02_PRODUITS_PHYSIQUES/Microphone/tests/test_final.wav
Normal file
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02_PRODUITS_PHYSIQUES/Microphone/tests/untitled.wav
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02_PRODUITS_PHYSIQUES/Microphone/tests/untitled.wav
Normal file
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Loading…
Reference in a new issue